Digital Logic Circuits & Gate Conversions

Let A = A₁A₀ and B = B₁B₀. The two numbers are equal when each bit matches: A₁ = B₁ and A₀ = B₀. The equality of two bits is the XNOR function, X ⊙ Y = XY + X′Y′.

Each XNOR is a pair of parallel branches; the two XNORs are wired in series so the coil energises only when both bit-pairs match.

|--[ A1]--[ B1]--+--[ A0]--[ B0]--+----( F )--|
|                |                |
|--[/A1]--[/B1]--+--[/A0]--[/B0]--+

Multiplying A = A₁A₀ by B = B₁B₀ gives a product P of up to four bits, P₃P₂P₁P₀. The four AND-gate partial products are added column by column.

So the circuit needs four AND gates for the partial products, one half-adder to produce P₁ and the carry C₁, and a second half-adder to produce P₂ and P₃.

Inputs are A (minuend), B (subtrahend) and B_in (borrow-in); outputs are D (difference) and B_out (borrow-out).

Building it from NAND only

Every gate is replaced by its NAND equivalent: X′ = X NAND X; X·Y = (X NAND Y) NAND (X NAND Y); X+Y = (X NAND X) NAND (Y NAND Y); and an XOR is built from four NANDs. The complete full subtractor uses roughly 14 NAND gates.

A 1-to-2 decoder has one address input A and two outputs; exactly one output is high at a time. Y₀ = A′ and Y₁ = A.

|---[/A]----------------( Y0 )---|
|---[ A]----------------( Y1 )---|

Three address inputs A, B, C drive eight outputs Y₀…Y₇. Output Y_n is high only when the binary value of ABC equals n, so each output is one unique product term.

|---[/A]---[/B]---[/C]----( Y0 )---|
|---[/A]---[/B]---[ C]----( Y1 )---|
|---[/A]---[ B]---[/C]----( Y2 )---|
|---[/A]---[ B]---[ C]----( Y3 )---|
|---[ A]---[/B]---[/C]----( Y4 )---|
|---[ A]---[/B]---[ C]----( Y5 )---|
|---[ A]---[ B]---[/C]----( Y6 )---|
|---[ A]---[ B]---[ C]----( Y7 )---|

A 4-bit binary value ranges 0–15, but one BCD digit only covers 0–9. For values 10–15 a two-digit BCD result is needed, produced with the “add-3” (double-dabble) method.

Let the binary inputs be I3 I2 I1 I0, and let X flag a value of 10 or more:

In ladder, X is detected on one rung; an ADD instruction adds 0110 to the lower nibble when X is true and the tens digit is set to 1. If a result ever falls outside 0–9, the program does not use don’t-cares — it simply moves on to process the next incoming number.

The two-bit input N takes values 0, 1, 2, 3, whose squares are 0, 1, 4, 9 — all single digits, so one seven-segment display suffices.

Simplifying each segment column gives:

In the set-dominant version, Q seals itself on through its own contact and is broken only by R; pressing S forces Q high. A second rung simply mirrors the inverse of Q to a separate coil so the complement Q′ is also available.

|---[ S ]---+----[/R]----+-------( Q  )--|
|           |            |
|---[ Q ]---+            |
|
|---[/Q]------------------------( Q' )--|

This is a T (toggle) flip-flop — each rising edge of the trigger flips the output. A one-shot rising (OSR) instruction turns each press into a single-scan pulse, which is routed to SET if Q is currently OFF, or to RESET if Q is currently ON.

|---[OSR T]---[/Q]----------------( SET )--|
|---[OSR T]---[ Q]----------------( RST )--|
|---[ SET ]---+----[/RST]---------( Q   )--|
|             |                   |
|---[ Q  ]----+-------------------+

De Morgan’s law gives the key substitution: NOR(X,Y) = (X + Y)′ = X′·Y′. Replace each NOR by an AND of inverted inputs, and keep each NOT as-is.

As a worked example, take a two-stage NOR chain F = NOR(NOR(A,B), C):

The equivalent basic-gate circuit is therefore an OR gate on A and B, an inverter on C, and an AND gate combining the two.

Each basic function has a fixed universal-gate substitution:

For example, F = A·B + C in NAND-only form: form AB with two NANDs, invert C with one NAND, then combine — about four NAND gates in total, functionally identical to the original.

From the truth table, F = 1 at minterms 3, 6, 7, 11, 12, 13, 14, 15. Plotting these gives the map below.

Grouping gives a compact sum-of-products — each term is simply a pair of adjacent bits both being 1:

|---[ A ]---[ B ]---+----( F )--|
|                   |
|---[ B ]---[ C ]---+
|                   |
|---[ C ]---[ D ]---+

The three-variable XOR is the odd-parity function: F = A ⊕ B ⊕ C is 1 whenever an odd number of inputs are 1.

Its sum-of-products expansion is F = A′B′C + A′BC′ + AB′C′ + ABC — the four rows where the count of 1s is odd.